WHAT OPENINGS DO WE CURRENTLY HAVE ?
We’re always on the lookout for highly driven and enthusiastic engineers for permanent roles. We are certain that EDIC Semicon culture is shaped by its employees. EDIC Semicon provides a professional and engaging work environment, as well as a diversity of development possibilities that encourage employees to reach their full potential.
Here are our available FULL-TIME positions
- Understanding the high-level specification and requirements of functional units of Interconnect products.
- Define the Micro-architecture for an unit
- Develop Verilog RTL logic design for the unit
- Collaborate with verification team on the test plan development for the blocks and verification closure
- Debug functional or performance issues with the RTL using simulation and debug tools
- Analyze synthesis/timing reports, identify and address critical areas to meet the PPA targets
- Experience with various aspects of digital verification such as test automation, code and functional coverage, constraint randomization, system Verilog assertions, and performance.
- SOC/Subsystem/IP DV, Debugging, problem solving
- Experience with Verilog/System Verilog, digital simulation.
- Experience with Perl, Python, or similar scripting language.
- Exposure to UVM is desired.
- Experience with AMBA bus protocols
- Experience with C/C++, assembly language.
- Knowledge of low power design concepts and power management is a big plus.
- Knowledge of computer architecture, cache concepts and digital design fundamentals.
- Prior knowledge on ARM Coresight ,Peripherals, Debug blocks, JTAG verification is an added advantage.
- Responsible for block level floorplan/Powerplan/Physical design and
- Signoff closure in STA/PDN/FV/CLP and PV.
- Should be well versed with ICC2/Innovus, Primetime and Calibre/ICV.
- Working with the frontend team in understanding the constraints at block level.
- Working with the DFT team to understand the DFT constraints and scan architecture at block level
- Automating the tasks with new scripts/flows that are needed for customizing the existing flow or to improve the existing flow.
- Synthesis, Static Timing Analysis and LEC of SoC/Cores
- Full chip and block level timing closure, IO budgeting for blocks
- Logical equivalence check between RTL to Netlist and Netlist to Netlist
- Knowledge of low-power techniques including clock gating, power gating and MV designs
- ECO timing flow
- Proficient in scripting languages (TCL and Perl).
- Expertise in Synopsys/Cadence Synthesis tool
- Expertise with STA with prime time
- Good Experience in synthesis timing closure and interactions with DFT and PD.
- Expertise in Low power flows for CLP, UPF ( Cadence low power, Unified power format)
- Experience in formal verification with Cadence LEC
- Expertise in ECO flows
- Experience in Spyglass Lint/CDC checks and waiver creation
- Experience in RTL HDL languages Verilog/VHD
- Understanding of RTL to GDS flow
- Expertise in Perl, TCL language
- In depth knowledge of DFT concepts
- In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis
- Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations
- Expertise in scripting languages such as perl, shell, etc.
- Experience in simulating test vectors
- Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TK, TetraMax)
- Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus
- Experience with physical verification checks DRC, LVS, Antenna, ERC, PERC, ESD etc.
- Experience in PnR tools like ICC/Innovus with regards to physical convergence must.
- Understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre and ICV.
- Good overall understanding of the Custom IC design flow.
- Good understanding of layouts and overall backend tool flow would be beneficial.
- Own and execute PV activities at the Top/Block level.
- Work closely with PD team in addressing their PV issues and also suggest solutions to them.
- Work with CAD team in refining the existing flows/methodologies and to resolve the issues
- Should be able to understand system level environment
- Planning Test strategy, creating test plan and test code development to address functional and performance requirements of the IPSubsystem.
- Experience with HDL languages (Verilogsystemverilog and VHDL) andor working knowledge of C, C++ is a must.
- Expertise in using compiler and debugging tools like GHS, Lauterbach
- HW debugging skills, FPGA debugging using chipscope etc.
- Expertise in using validation environment test equipment e.g. Logic Analyzers, Oscilloscope, Protocol Analyzers etc.
- Experience in working on ARM core architectures would be an advantage.
- Exposure to Xilinx Ultrascale device architecture and designing for the device will be an advantage.
